1. Field of the Invention
This invention relates to methods of manufacturing semiconductor devices having a porous structure and voids (air-gaps), and particularly relates to methods that involve selectively etching a sacrificial film.
2. Description of the Related Art
In recent years, semiconductor devices have become faster and more highly integrated and resistance-capacitance (RC) coupling delays have become a large factor in signal processing time. RC delays can be decreased by reducing wiring capacitance. One way to do this is to use low dielectric constant materials such as fluorine-doped SiO2, porous SiO2, an organic film or a porous film, etc. However, these materials have not been put to practical use because of problems such as processing difficulty and insufficient heat-resistance, which can increase the complexity of the integration processes and lower device reliability. Although, fluorinated silicon glass (FSG) is in production for 130 nm node technology, but for 90 nm and smaller nodes, low-k dielectrics with k≦3 are desired for manufacturing future semiconductor devices.
It is projected that high volume manufacturing of faster logic and other devices with 45 nm or lower nodes interconnect structures will require extreme low-k, such as k≦2.4.
The low-k interlayer dielectrics (ILDs) for 65 nm or lower nodes require not only low k values but also superior mechanical properties, thermal stability, and applicability to integration processes with copper for Dual Damascene structures. These integration processes are disclosed in U.S. Pat. No. 6,440,838 and U.S. Pat. No. 6,440,861, for example. Further, it is preferable to adapt currently available materials, tools, and apparatuses to high volume manufacturing.